Sense amplifier for single device per bit mosfet memories

ABSTRACT

A HIGHLY EFFICIENT SENSE AMPLIFIER FOR METAL OXIDE CHIP MEMORY ARRAYS CAN BE BUILT BY USING A PAIR OF CROSS-COUPLED SENSING MOSFETS CONNECTED IN A RACING MODE BETWEEN A BIT LINE CAPACITANCE AND A PRECHARGE STORAGE CAPACITANCE TO PRODUCE A FULL &#34;1&#34; OR FULL-&#34;0&#34; BIT LINE CONDITION RESPONSIVE TO THE CAPACITIVE INFORMATION CHARGE STORED IN AN ADDRESSED BIT, AND TRANSFERRED TO THE BIT LINE WHICH CONDITION CAN SERVE BOTH AS A RESTORNIG SIGNAL AND AS A READOUT SIGNAL. BIT LINE CAPACITANCE CAN BE REDUCED, AND A SEPARATE PRECHARGE STORAGE CAPACITANCE ELIMINATED, BY CONNECTING EACH OF THE CROSS-COUPLED MOSFETS TO HALF OF THE BIT LINE, AND USING THE PRECHARGE STORAGE CAPACITANCE.

United States Patent 1 isn Inventor Alton O. Chrktensen Houston, Tex.

Appl. No. 839,720

Filed July 7, 1969 Patented June 28, 1971 Assignee Shell Oil Company New York,

Continuation-impart of application Ser. No. 827,193, May 23, 1969.

SENSE AMPLIFIER FOR SINGLE DEVICE PER BIT [56] Relerences Cited UNITED STATES PATENTS 3,292,008 12/1966 Rapp 340/173 3,363.1l5 1/1968 Stephenson 340/173 Primary ExaminerTerrell W. Fears Attorneys-T. E. Bieber and J. H. McCarthy ABSTRACT: A highly efficient sense amplifier for metal oxide silicon chip memory arrays can be built by using a pair of cross-coupled sensing MOSFETs connected in a racing mode between a bit line capacitance and a precharge storage capacitance to produce a fulll or full-0" bit line condi- MOSFET MEMORIES tron responsive to the capacitive information charge stored in 24 claims 4 Drawing an addressed bit, and transferred to the bit line which condi- U.S.CI 340/173, tion can serve both as a restoring signal and as a readout 307/238, 307/279 signal. Bit line capacitance can be reduced, and a separate Int. Cl G 1 16 11/40, precharge storage capacitance eliminated, by connecting each H03k 3/286 of the cross-coupled MOSFETs to half of the bit line, and Field of Search 340/ l 73; using the line capacitance of the idle half of the bit line as the 307/238, 279 precharge storage capacitance.

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TO OTHER Y ADDRESS GATES DATA OUT READ l 32\ Y ADDRESS :|T[ 1--- DATA m N RE m m 7 m m A E VT w N N S R 1m MM 0 4 H 1 W A, A G o M N W W D S S m E E m m R D m X X W @ENSII AMPLIFIER FOR SINGLE DEVICE PER BIT MOSFET MEMORIES This application is a continuation-in-part of pending application Ser. No. 827,]93, filed May 23, I969.

BACKGROUND OF THE INVENTION This invention relates to the single device per bit metal oxide silicon chip memory disclosed in the copending application Ser. No. 825,257, filed May l6, I969, entitled SINGLE RAIL MOSFET MEMORY WITH CAPACITIVE STORAGE. In that application, a single device per hit metal oxide silicon field effect transistor MOSF ET) memory is disclosed in which informational charge increments are transferred between the cell capacitance of an addressed memory cell and a bit line capacitance, and reading, writing, and restoring is done by conventional external means. It is of course highly desirable to incorporate the reading, writing, and restoring circuitry on the memory chip itself, and it is further desirable to make the read amplifier as insensitive as possible to variations in the absolute bit line voltage or in the informational charge increments impressed on the bit line, or to parameter variations between individual MOSFETs on the chip.

SUMMARY OF THE INVENTION The present invention provides a solution to the aforesaid problem by providing a MOSFET read-write-restore circuit capable of being formed on the memory chip itself and using a pair of cross-coupled MOSFETs connected in a racing mode between a precharge capacitance and the bit line capacitance to transform a small bit line voltage variation resulting from a charge transfer into a full-1" or full-" data output and restoration signal, regardless of the absolute values of the voltages involved.

The circuit of this invention has the further advantage over the circuit of the prior application that the write time of the cycle precedes the read time, and that it is consequently possible to perform a writing and reading operation on a given cell in the same cycle.

Furthermore, in accordance with a further aspect of this invention, the bit line capacitance (which should be as small as practically possible) can be cut in half by splitting the bit line in two and selectively addressing one or the other half of the bit line. This system has the further advantage of dispensing with the necessity for a separate precharge capacitance, as the bit line capacitance of the idle bit line half can be used as the precharge capacitance.

Finally, the invention makes it practical to use a separate read-write-restore circuit for each column of the memory array, so that the entire memory can be exercised by exercising each row once in sequence. In a typical l024-bit MOSFET memory, in which each bit needs to be exercised at least once every millisecond, the 32-volt refresh sequence (which represents wasted working time) is a considerable improvement over the 256-cycle refresh sequence of the copending application.

It is therefore the object of the invention to provide a readwrite-restore circuit suitable for incorporation in a singledevice-per-bit MOSFET memory chip.

It is a further object of the invention to provide a circuit of the type described which translates even the minutest voltage increment in the bit line as a result of information transfer into a full- I or 0 output.

It is yet another object of the invention to provide a circuit of the type described which automatically restores during each cycle all bits which have the same X address as the addressed bit.

It is still another object of the invention to provide a circuit of the type described in which writing and reading can be accomplished on an addressed bit in the same cycle.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a fragmentary circuit diagram showing the device of this invention and its relation to a single-bit-per-device MOSFET memory;

FIG. 2 is the timing diagram for the circuit of FIG. I;

FIG. 3 is a fragmentary circuit diagram showing a further embodiment of the device of this invention; and

FIG. 4 is the timing diagram for the circuit of FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENT A standard l024-bit random access memory is typically arranged in a square array of 32 columns by 32 rows. Each column is identified by a specific X address, and each row is identified by a specific Y address.

In FIG. I the reference numeral I0 designates one of sixteen memory cells which make up the left half of a given row of such an array. Each cell represents one bit of information.

These memory cells, of which only one is shown for clarity, all have a common Y address but different X addresses, and the information therein, represented by the charge on internal capacitance I4, is transferred to the common bit line half 16 when the cell is addressed by a coincidence of the proper X and Y addresses.

The reference numeral 12 designates one of the other sixteen cells with the same Y address as the previously mentioned cells. The information stored in the internal capacitance B4 of an addressed one of the cells represented by cell 12 is transferred to the common bit line half I8. It will be seen that this arrangement divides the bit line for a given Y address into two halves 16, I8 for a purpose hereinafter described, and that the bit line capacitance is thus also divided into two halves 20, 22.

The nature and operation of the device of this invention is best understood by following an operational cycle of the timing diagram shown in FIG. 2. At the beginning of the cycle, one of the bit line capacitance 20,22 is at ground, and the other at logic I from the previous cycle. Consequenfly, one of the MOSFETs 28, 30 is enabled, and the other is blocked. Let us assume that 20 is at ground and that 22 is at logic 1."

The initiation of the clock pulse b, now enables MOSFETs 24 and 26, and the simultaneous initiation of I applies logic 1" to the common connection of MOSFETs 28 and 30. The application of logic I" to bit line half I6 simultaneously through both of the enabled MOSFETs 24, 28 rapidly charges capacitance 20 to a full I" level of, for example, about 8 volts. The impression of a l" on bit line half I6 enables MOSFET 30, and the circuit is now ready to receive information.

Following the cessation of the 4 and 0, pulses, the circuit is addressed with the gates of both MOSFETs 28 and 30 at logic For the purposes of this description, let it be assumed that the address selected is the address of cell 12. The address pulse (FIG. 2) enables MOSFETs 32 and 34, the former being responsive to the Y portion, and the latter to the X portion of the address of cell 12. The enabling of MOSFET 34 causes capacitor 14 to be connected to bit line half 18. Assuming that the information stored in cell 12 is a 0" (Le. no charge on capacitance 14 of cell 12), capacitance 14 is charged by the much larger bit line capacitance 22. As a result, the line voltage in bit line half I3, and hence the potential applied to the gate of MOSFET 28, will decrease slightly. It will be seen that the advantage of splitting the bit line into two halves 16, 18 is the reduction of the bit line capacitance from which the capacitance I4 draws its charge, and a consequent increase in the potential difference applied to the gate of MOSFET 28.

Had the information in cell 12 been a I, no charge transfer would have taken place between line capacitance 22 and cell capacitance 14 of cell 12. However, the total capacitance charged to the l level in bit line half 18 (cell capacitance I4 plus line capacitance 22 plus the gate capacitance of MOSFET 28) is greater than the 1 "-charged capacitance in bit line half 16 (line capacitance 20 plus gate capacitance of MOSFET 28).

Immediately upon the cessation of the I and 4), pulses, MOSFETs 24 and 26 cease conducting, and bit line halves I6, 18 are connected to ground through MOSFETs 28 and 30, respectively. MOSFETs 28 and 30 are now connected in a "race" mode, i.e. they both discharge their gate capacitance to ground level until one of them reaches the threshold voltage. The first MOSFET to reach threshold voltage ceases to conduct and prevents further discharge of the gate of the opposing MOSFET. Consequently, the opposing MOSFET continues to conduct until the gate capacitance of the first MOSFET is completely discharged to ground.

Thus, if the line voltage on bit line half I8 is lower than that on bit line half 16 (a readout from cell 12), the gate of MOSFET 28 starts closer to threshold and reaches threshold first. On the other hand, if the line voltages are equal (a I readout from cell 12), the slower discharge rate of bit line half 18, due to the total capacitance on that side being larger than that on the side of bit line half 16, causes the gate of MOSFET 30 to reach the threshold voltage first. Consequently, ifcell 12 holds a 1" when addressed, bit line half 18 remains at a threshold voltage level, whereas bit line half 16 continues to discharge and eventually reaches ground level.

When the second Q pulse now occurs, MOSFET 30 is blocked, and line capacitance 22 is recharged to a full I level through MOSFET 26. The potential in bit line half 16 also rises, the absence of a D, pulse at this time causes a voltage divider action through MOSFETs 24 and 28.

MOSFETs 24, 28 (and 26, 30) may be so proportioned with respect to one another that the potential of bit line half 16 is kept below threshold regardless of the duration of the 4 or else they may all be equal, and the duration of the 9, pulse may be kept short enough to prevent the potential of bit line half 16 from reaching threshold.

Following the end of the second Cl pulse, MOSFETs 24, 26 are blocked, and bit line half 16 discharges back to ground level through MOSFET 28. Bit line half 18 remains at logic 1" because MOSFET 30 is blocked.

Writing is accomplished by enabling the write gate 42 during the write pulse in the presence of input data. The low-impedance input data easily overrides the effect of cell capacitance 14 on the line voltage, and the input data is thus substituted for the date stored in cell 12. It should be noted that the write pulse occurs before the read pulse, and it is therefore possible to write, and to read the just written data, in the same operational cycle.

Inasmuch as the cell capacitance 14 of cell 12 remains connected to bit line half I8 throughout the address pulse, it follows the line voltage changes in bit line half 18. At the end of the address pulse, the cell capacitance I4 is therefore in a restored (or newly written) full" I "or full "0" condition.

It will be noted that if the X portion of the address of cell 12 is present during the address pulse, cell 12 will go through a destroy-and-restore cycle of information transfer even though the absence of the Y portion of the address prevents reading or writing. Consequently, all cells with a given X address are exercised each time any one ofthem is exercised.

Inasmuch as the charges on the cell capacitances l4 tend to gradually leak off, it is necessary to periodically (about once every millisecond) refresh the information stored in the bits of nonaddressed columns. This can be accomplished by providing a cycle counter (not shown) driven by, e.g., the b, pulses, which periodically interrupts the random operation of the array and exercises all X addresses in sequence without reading or writing. For a l024-bit array in a 32 32-bit configuration with a 100 nanosecond cycle, the 32-cycle refresh sequence (which is wasted time as far as the computer is concerned) would consume 3200 nanoseconds per millisecond, or an insignificant 0.32 percent of the total operating time.

Depending on the X address of an addressed memory cell, it may lie on bit line half 16 or on bit line half I8. The X address is conventionally arrived at by feeding binriry address component signals X,, X,, X,, X,,, and X to a series of decoders (not shown), one for each X address. Each decoder is arranged to produce an output only in the presence of a specific combination of address component signals. Conventionally, the X addresses in the right half of a 32-column array each have an X component, while those in the left half do not. Consequently, the proper selection of bit line half 16 or 18 for a given X address is readily made by applying X to selection gate 44, and Y to the selection gate 46.

It is. of course, possible to connect the entire bit line to one side of the sense amplifier, e.g. to the junction between MOSFETs 26, 30. This would dispense with the necessity for the selection gates 44, 46. On the other hand, it would necessitate the provision ofa capacitive pad connected to the junction between MOSFETs 24, 28, ofa capacitance equal to the line capacitance of the bit line, to replace the line capacitance of the idle bit line half in the preferred embodiment. Also, as pointed out hereinabove, the decrease in the active bit line capacitance resulting from the splitting of the bit line makes the circuit parameters less critical.

FIG. 3 shows a modification of the circuit described above in which a single MOSFET 50 is substituted for the pair of MOSFETs 24 and 26 of FIG. 1. Since a pair of MOSFETs 24 and 26 is required for each of the 32 rows of a memory constructed as shown in FIG. 1, and only one MOSFET 50 is required for each of the 32 rows of a memory constructed as shown in FIG. 3, a potential saving of some 32 MOSFETs per memory is offered by using the construction shown in FIG. 3. However, as will be seen when the operation of the device shown in FIG. 3 is more fully discussed, one or more additional MOSFETs will be required for each complete memory constructed as shown in FIG. 3 than are required for a complete memory constructed as shown in FIG. 1. Thus the potential saving will be reduced by one or two MOSFETs. A saving in number of MOSFETs per memory will obviously enable the memory to be more easily placed on a chip of given size. It will also reduce the fabrication cost, not so much by eliminating the cost of formation of such MOSFETs, as by improving the yield which will vary inversely with the total number of MOSFETs per chip required for a particular memory.

As will be seen from the following description of the operation of the device shown in FIG. 3, this modification will also simplify the operation of the memory by requiring only a single G clock pulse during each cycle of operation rather than the double 1 pulse required in the operation of the device shown in FIG. 1. In addition the 4 clock pulse is available during the readout portion of the cycle to charge the inherent capacitance of the output line thus providing more reliable operation and readings even where such output line is of unusual length.

Referring now to FIG. 4 it will be seen that the read, address, and write pulses of the cycle of operation of the device shown in FIG. 3 are the same as those shown in FIG. 2 for the device of FIG. 1. However, since the MOSFET 50 of the device shown in FIG. 3 is connected to MOSFETs 28 and 30 through MOSFETs 46 and 44, respectively, it is necessary to apply a pulse to the gates of both 46 and 44 during the portion of the 4 pulse which occurs during the first, or precharge, time interval of the cycle of operation. Such pulses may be readily derived from a single FARMOST inverter circuit such as that described in patent No. 3,502,908 which issued from application Ser. No. 787,067, filed Dec. 26, 1968 requiring one or two MOSFETs for the complete memory. Such inverter circuits could be precharged by the 1 pulse, for example, which is coincident with that portion of the 1 pulse which occurs during the first time interval of the cycle of operation. FIG. 4 shows the X and Y, pulses required to be applied to the gates of 44 and 46, respectively, of the device shown in FIG. 3 if cell 12 is addressed as in the example described hereinabove with respect to FIG. 1. The continuation of the X pulse on the gate of 44 may, of course, be derived from the X address after the end of the 41 pulse and that portion of the 1 pulse which occurs during the first time interval of the cycle.

Thus, at the beginning of the cycle let us assume that bit line capacitance is at ground and 22 is at logic I." MOSFET 50 is enabled by the b, clock and the I clock pulse can be used to enable MOSFETs 44 and 46 through appropriate precharged inverter circuits as suggested above.

The application of both 4), and I pulses to capacitance 20 of bit line half 16 through MOSFETs 46 and 28 respectively rapidly charges it to full logic l level which enables MOSFET making the circuit ready to receive information.

Following the cessation of the q and I), pulses, MOSFETs 46 and 50 cease conducting and cell 12, for example, of the circuit is addressed by enabling MOSFETs 32, 34 and 44. The operation of the circuit of FIG. 3 through the "write" and "race" portions of the cycle proceeds as described with respect to the circuit shown in FIG. 2. However, during the read portion of the cycle the 9, clock pulse resumes, enabling MOSFET 50. It will be seen that the 4), clock pulse will be connected to the output line through MOSFETs 32 and and is thus available to help capacitances 22 and 14 charge the output line in the event that logic I" is stored in cell 12. The availability of the 0, pulse will also avoid degradation of the logic l charge stored in cell 12. If logic 0" is stored in cell 12, it will have lost the "race" with the opposing side of the bit line and MOSFET 30 will be enabled, thus connecting D, to ground through MOSFET 30 and the 9, input which is at ground during the read" portion of the cycle, thus giving a logic 0" output.

As pointed out above, the double 4 pulse required by the circuit shown in FIG. 1 is not required by the circuit shown in FIG. 3. This also means that the voltage divider action described with respect to MOSFETs 24 and 28 (or 26 and 30) of FIG. 1 during the second l pulse is unnecessary, thus causing the fabrication of the circuit shown in FIG. 3 tobe somewhat simpler and less expensive than the fabrication of the circuit shown in FIG. I. The periodic refresh sequence in which all X addresses are exercised in sequence to restore their charge is, of course, possible in the circuit of FIG. 3 as in the circuit of FIG. 1. The periodic refresh sequence in which all X addresses are exercised in sequence to restore their charge is, of course, possible in the circuit of FIG. 3 as in the circuit of FIG. 1. Similarly the various modifications suggested with respect to the circuit of FIG. 1 are also possible with respect to the circuit of FIG. 3.

lclaim:

l. A MOSFET sense amplifier for sensing informationrepresenting charge transfers to and from a memory capacitance, comprising:

a. a pair of cross-coupled MOSFETs having a common source connection and having their gates connected to each other's drain;

b. a pair of capacitive means each connected to the drain of one ofsaid MOSFETs;

. precharge means arranged to precharge said capacitive means during a first period of time to a substantially equal energy level sufficient to enable both of said MOSFETs;

d. address means for rendering said energy levels of said capacitive means unequal following said precharge by connecting said memory capacitance to one of said capacitive means; and

e. means arranged to drive said capacitive means toward ground through the source-drain circuit of said MOSFETs during a subsequent second time period, whereby said MOSFETs are caused to operate in a race mode which results in the capacitive means with the greater energy level being brought to threshold voltage, and the capacitive means with the lesser energy level being brought to ground.

2. A device according to claim I, further including means for driving said capacitive means with the greater energy level to a predetermined potential greater than said threshold voltage while generally maintaining said capacitive means with the lesser energy level at ground, during a subsequent third time period.

3. A device according to claim 1, further including write means operable following said precharge to override the effect of said address means by connecting said one of said capacitive means to a low-impedance data source.

4. A memory device of the capacitive storage type, comprising:

a. an array of capacitive-storage memory cells arranged in rows having a common Y address, and columns having a common X address;

b. a plurality of bit line'means, one for each row;

c. X address means operative during clocked address pulses for connecting each of said memory cells in a selected column to the bit line means of its row; and

d. a plurality of sense amplifier means, one for each row,

each including:

i. A pair of cross-connected MOSFETs having their drains connected to each other's gate and to capacitive means; and

ii. a pair of charging gate means connected between a source of first clock pulses and the respective drains of said cross-connected MOSFETs, and gated by said first clock pulses;

iii. the sources of said cross-connected MOSFETs being connectedto a source of second clock pulses;

c. said bit line means being connected to the drain of one of said cross-connected MOSFETs of the sense amplifier in the same row.

5. The device of claim 4, in which said capacitive means connected to the MOSFET drain to which said bit line means is connected is the bit line capacitance.

6. The device of claim 4, in which said first clock pulses have twice the repetition rate of said second clock pulses and said address pulses, and said address pulses being immediately following alternate ones of said first clock pulses, straddle the other ones of said first clock pulses, but do not occur during said second clock pulses.

7. The device of claim 4, further comprising data input and data output means common to the entire array; and a plurality of Y address gate means, one for each row, said Y address gate means being selectively enabled during said address pulses and being connected between said data input and output means and said bit line means.

8. The device of claim 7, further comprising read gate means gated by clocked read pulses and connected between said data output means and said Y address gate means; and write gate means gated by clocked write pulses and connected between said data input means and said Y address gate means.

9. The device of claim 8, in which said read pulses occur substantiallyduring the portion of said address pulses following the end of said alternate ones of said first clock pulses.

10. The device of claim 8, in which said write pulses occur substantially during the portion of said address pulses preceding the beginning of said alternate ones of said first clock pulses.

11. The device of claim 4, in which each said bit line means is divided into two separate halves, one half being connected to the drain of one of the crossconnected MOSFETs of its amplifier, and the other half being connected to the drain of the other cross-connected MOSF ET of the same amplifier.

12. The device of claim 11, in which said capacitive means are the respective line capacitances of the two halves of the bit line means.

13. The device of claim ll, further comprising data input and output means, and bit line half selection gate means interposed between each of said bit line halves and said data input and output means, and gated, respectively, by third and fourth pulses selectively occurring coincidentally with said address pulses.

14. The device of claim 13, in which said third and fourth pulses are mutually exclusive and are component parts of all the X addresses of the cells associated with the selected bit line half.

15. A memory device of the capacitive storage type, comprising:

a. an array of capacitive-storage memory cells arranged in rows having a common Y address, and columns having a common X address;

. a plurality of bit line means, one for each row;

c. X address means operative during clocked address pulses for connecting each of said memory cells in a selected column to the bit line means ofits row; and

d. a plurality of sense amplifier means. one for each row,

each including:

i. a pair of cross-connected MOSFETs having their drains connected to each other's gate and to capacitive means;

ii. a third MOSFET having its drain connected to the drain of one of said cross-connected MOSFETs and a fourth MOSFET having its drain connected to the drain of the other of said cross-connected MOSFETs;

iii. a charging gate means connected between a source of first clock pulses and the sources of both said third and said fourth MOSFETs, and gated by said first clock pulses; and

iv. means connected to the gates of said third and fourth MOSFETs for gating both during a first portion of said first clock pulse and only a selected one during at least a second portion of said first clock pulse;

v. the sources of said cross-connected MOSFETs being connected to a source of second clock pulses;

e. said bit line means being connected to the drain of one of said cross-connected MOSFETs of the sense amplifier in the same row.

16. The device of claim in which said capacitive means connected to the MOSFET drain to which said bit line means is connected is the bit line capacitance.

17. The device of claim 15, further comprising data input and data output means common to the entire array; and a plurality of Y address gate means. one for each row, said Y address gate means being selectively enabled during said address pulses and being connected between said data input and output means and said bit line means.

18. The device of claim 17, further comprising read gate means gated by clocked read pulses and connected between said data output means and said Y address gate means; and write gate means gated by clocked write pulses and connected between said data input means and said Y address gate means.

l9. The device of claim 18, in which said read pulses occur during said second portion of said first clock pulses after said second clock pulse has ended.

20. The device of claim IS in which said write pulses occur between said first clock pulses.

2l. The device of claim IS, in which each said bit line means is divided into two separate halves, one half being connected to the drain of one of the cross-connected MOSFETs of its amplifier, and the other half being connected to the drain of the other cross-connected MOSFET of the same amplifier.

22. The device of claim 15, in which said capacitive means are the respective line capacitances of the two halves of the bit line means.

23. The device of claim 21, further comprising input and output means connected to the sources of both said third and said fourth MOSFETs.

24. The device of claim 23, in which said means connected to the gates of said third and fourth MOSFETs gates a selected one thereof by generating a pulse which is a component part of all X addresses of the cells associated with a selected bit line half.

Disclaimer 3,588,844.Alt0n O. Christensen, Houston, Tex. SENSE AMPLIFIER FOR SINGLE DEVICE PER BIT MOSFET MEMORIES. Patent dated June 28, 1971. Disclaimer filed June 20, 1977, by the assignee, Shell Oil Uompamy. Hereby enters this disclaimer to claims 1-14 of said patent.

[Oficz'al Gazette August 25, 1977.] 

